FIG. 3 shows a part of a semiconductor memory device circuit as the background art of this invention, i.e. one column of a CMOS DRAM having a serial access function. In FIG. 3, a bit line equalizer circuit, precharger circuit and the like are omitted, and only those circuit portions associated with data sensing and transfer are shown. Each bit line of a pair of bit lines BLN and BLN is connected with the same number of cells. A V.sub.PL line is a fixed electrode of a cell capacitor. The bit line pair BLN, BLN is pre-charged to 1/2 V.sub.cc. When a word line WL.sub.1 and WL.sub.2 is activated, the contents (data) of a cell which appear on one of the bit line pairs are compared with a reference voltage 1/2 V.sub.cc on the other of the bit line pair, and amplified by a sense amplifier. In sensing the data, a line SAN is first disabled and then a line SAP is activated. After a sufficient potential difference is obtained between the bit line pair BLN, BLN, a line CSL of a selected column is activated to transfer the data to data lines DQ and DQ. The data is read in this manner.
If the data is to be transferred to and stored in serial data registers, a transfer gate TRG common to all columns is activated to thereby transfer the data to the data register. At a cycle other than the transfer cycle, the transfer gate TRG takes a low level and is closed. In response to an external serial mode signal, serial gates SSL are sequentially activated to sequentially transfer and output the data in the data registers connected to respective columns, to serially input/output lines SI/O, SI/O.
As described above, according to the background art, a serial register is provided for each column to conduct serial access in the column direction.
The larger the memory capacity becomes, the smaller the pitch between columns becomes. It is therefore difficult to provide for each column a serial circuit portion such as serial registers. There is a tendency that a cell capacitance is made smaller, whereas the capacitance of the bit line pair BLN, BLN becomes large, mainly due to the addition of the serial circuit portion. Namely, the pitch between columns becomes large because it depends upon the serial circuit portion such as serial registers. It is therefore impossible to have a cell array with a highly efficient pattern. In addition, the read-out quantity of cell data becomes small and considerably deteriorates a sense margin.